The system is suitable for high-temperature reverse bias HTRB+/HTRB - and high-temperature gate bias testing HTGB and aging screening of SiC wafers of 8 inches and below; Block the entry of defective dies into the subsequent cutting, packaging, aging testing, and other processes earlier.

Suitable for high-temperature dynamic aging screening and lifespan testing of various packaging forms of analog, digital, and mixed signal integrated circuits, including ultra large scale integrated circuits such as SoC, MCU, Memory, and other IC devices.

Develop and design according to the requirements of AEC-Q101 standard, covering intermittent life test IOL and steady-state life test CFL for Si/SiC/GaN discrete devices such as diodes, transistors, MOSFETs, IGBT single tubes, etc; The system can intuitively monitor the Δ Tj of each DUT throughout the entire IOL test process.

Satisfy high-temperature reverse bias/gate bias testing (HTRB/HTGB) and high-temperature leakage current testing (HTIR) for various packaging forms of semiconductor discrete devices such as diodes, transistors, field-effect transistors, IGBT single tubes, and thyristors.